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vis.h
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1 /*
2  * Copyright (C) 2003 David S. Miller <davem@redhat.com>
3  *
4  * This file is part of FFmpeg.
5  *
6  * FFmpeg is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * FFmpeg is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with FFmpeg; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19  */
20 
21 /* You may be asking why I hard-code the instruction opcodes and don't
22  * use the normal VIS assembler mnenomics for the VIS instructions.
23  *
24  * The reason is that Sun, in their infinite wisdom, decided that a binary
25  * using a VIS instruction will cause it to be marked (in the ELF headers)
26  * as doing so, and this prevents the OS from loading such binaries if the
27  * current cpu doesn't have VIS. There is no way to easily override this
28  * behavior of the assembler that I am aware of.
29  *
30  * This totally defeats what libmpeg2 is trying to do which is allow a
31  * single binary to be created, and then detect the availability of VIS
32  * at runtime.
33  *
34  * I'm not saying that tainting the binary by default is bad, rather I'm
35  * saying that not providing a way to override this easily unnecessarily
36  * ties people's hands.
37  *
38  * Thus, we do the opcode encoding by hand and output 32-bit words in
39  * the assembler to keep the binary from becoming tainted.
40  */
41 
42 #ifndef AVCODEC_SPARC_VIS_H
43 #define AVCODEC_SPARC_VIS_H
44 
45 #define vis_opc_base ((0x1 << 31) | (0x36 << 19))
46 #define vis_opf(X) ((X) << 5)
47 #define vis_sreg(X) (X)
48 #define vis_dreg(X) (((X)&0x1f)|((X)>>5))
49 #define vis_rs1_s(X) (vis_sreg(X) << 14)
50 #define vis_rs1_d(X) (vis_dreg(X) << 14)
51 #define vis_rs2_s(X) (vis_sreg(X) << 0)
52 #define vis_rs2_d(X) (vis_dreg(X) << 0)
53 #define vis_rd_s(X) (vis_sreg(X) << 25)
54 #define vis_rd_d(X) (vis_dreg(X) << 25)
55 
56 #define vis_ss2s(opf,rs1,rs2,rd) \
57  __asm__ volatile (".word %0" \
58  : : "i" (vis_opc_base | vis_opf(opf) | \
59  vis_rs1_s(rs1) | \
60  vis_rs2_s(rs2) | \
61  vis_rd_s(rd)))
62 
63 #define vis_dd2d(opf,rs1,rs2,rd) \
64  __asm__ volatile (".word %0" \
65  : : "i" (vis_opc_base | vis_opf(opf) | \
66  vis_rs1_d(rs1) | \
67  vis_rs2_d(rs2) | \
68  vis_rd_d(rd)))
69 
70 #define vis_ss2d(opf,rs1,rs2,rd) \
71  __asm__ volatile (".word %0" \
72  : : "i" (vis_opc_base | vis_opf(opf) | \
73  vis_rs1_s(rs1) | \
74  vis_rs2_s(rs2) | \
75  vis_rd_d(rd)))
76 
77 #define vis_sd2d(opf,rs1,rs2,rd) \
78  __asm__ volatile (".word %0" \
79  : : "i" (vis_opc_base | vis_opf(opf) | \
80  vis_rs1_s(rs1) | \
81  vis_rs2_d(rs2) | \
82  vis_rd_d(rd)))
83 
84 #define vis_d2s(opf,rs2,rd) \
85  __asm__ volatile (".word %0" \
86  : : "i" (vis_opc_base | vis_opf(opf) | \
87  vis_rs2_d(rs2) | \
88  vis_rd_s(rd)))
89 
90 #define vis_s2d(opf,rs2,rd) \
91  __asm__ volatile (".word %0" \
92  : : "i" (vis_opc_base | vis_opf(opf) | \
93  vis_rs2_s(rs2) | \
94  vis_rd_d(rd)))
95 
96 #define vis_d12d(opf,rs1,rd) \
97  __asm__ volatile (".word %0" \
98  : : "i" (vis_opc_base | vis_opf(opf) | \
99  vis_rs1_d(rs1) | \
100  vis_rd_d(rd)))
101 
102 #define vis_d22d(opf,rs2,rd) \
103  __asm__ volatile (".word %0" \
104  : : "i" (vis_opc_base | vis_opf(opf) | \
105  vis_rs2_d(rs2) | \
106  vis_rd_d(rd)))
107 
108 #define vis_s12s(opf,rs1,rd) \
109  __asm__ volatile (".word %0" \
110  : : "i" (vis_opc_base | vis_opf(opf) | \
111  vis_rs1_s(rs1) | \
112  vis_rd_s(rd)))
113 
114 #define vis_s22s(opf,rs2,rd) \
115  __asm__ volatile (".word %0" \
116  : : "i" (vis_opc_base | vis_opf(opf) | \
117  vis_rs2_s(rs2) | \
118  vis_rd_s(rd)))
119 
120 #define vis_s(opf,rd) \
121  __asm__ volatile (".word %0" \
122  : : "i" (vis_opc_base | vis_opf(opf) | \
123  vis_rd_s(rd)))
124 
125 #define vis_d(opf,rd) \
126  __asm__ volatile (".word %0" \
127  : : "i" (vis_opc_base | vis_opf(opf) | \
128  vis_rd_d(rd)))
129 
130 #define vis_r2m(op,rd,mem) \
131  __asm__ volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) )
132 
133 #define vis_r2m_2(op,rd,mem1,mem2) \
134  __asm__ volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) )
135 
136 #define vis_m2r(op,mem,rd) \
137  __asm__ volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) )
138 
139 #define vis_m2r_2(op,mem1,mem2,rd) \
140  __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) )
141 
142 static inline void vis_set_gsr(unsigned int _val)
143 {
144  register unsigned int val __asm__("g1");
145 
146  val = _val;
147  __asm__ volatile(".word 0xa7804000"
148  : : "r" (val));
149 }
150 
151 #define VIS_GSR_ALIGNADDR_MASK 0x0000007
152 #define VIS_GSR_ALIGNADDR_SHIFT 0
153 #define VIS_GSR_SCALEFACT_MASK 0x0000078
154 #define VIS_GSR_SCALEFACT_SHIFT 3
155 
156 #define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1)
157 #define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1)
158 #define vis_st32(rs1,mem) vis_r2m(st, rs1, mem)
159 #define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2)
160 #define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1)
161 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1)
162 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem)
163 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2)
164 
165 #define vis_ldblk(mem, rd) \
166 do { register void *__mem __asm__("g1"); \
167  __mem = &(mem); \
168  __asm__ volatile(".word 0xc1985e00 | %1" \
169  : \
170  : "r" (__mem), \
171  "i" (vis_rd_d(rd)) \
172  : "memory"); \
173 } while (0)
174 
175 #define vis_stblk(rd, mem) \
176 do { register void *__mem __asm__("g1"); \
177  __mem = &(mem); \
178  __asm__ volatile(".word 0xc1b85e00 | %1" \
179  : \
180  : "r" (__mem), \
181  "i" (vis_rd_d(rd)) \
182  : "memory"); \
183 } while (0)
184 
185 #define vis_membar_storestore() \
186  __asm__ volatile(".word 0x8143e008" : : : "memory")
187 
188 #define vis_membar_sync() \
189  __asm__ volatile(".word 0x8143e040" : : : "memory")
190 
191 /* 16 and 32 bit partitioned addition and subtraction. The normal
192  * versions perform 4 16-bit or 2 32-bit additions or subtractions.
193  * The 's' versions perform 2 16-bit or 1 32-bit additions or
194  * subtractions.
195  */
196 
197 #define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd)
198 #define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd)
199 #define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd)
200 #define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd)
201 #define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd)
202 #define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd)
203 #define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd)
204 #define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd)
205 
206 /* Pixel formatting instructions. */
207 
208 #define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd)
209 #define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd)
210 #define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd)
211 #define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd)
212 #define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd)
213 
214 /* Partitioned multiply instructions. */
215 
216 #define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd)
217 #define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd)
218 #define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd)
219 #define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd)
220 #define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd)
221 #define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd)
222 #define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd)
223 
224 /* Alignment instructions. */
225 
226 static inline const void *vis_alignaddr(const void *_ptr)
227 {
228  register const void *ptr __asm__("g1");
229 
230  ptr = _ptr;
231 
232  __asm__ volatile(".word %2"
233  : "=&r" (ptr)
234  : "0" (ptr),
235  "i" (vis_opc_base | vis_opf(0x18) |
236  vis_rs1_s(1) |
237  vis_rs2_s(0) |
238  vis_rd_s(1)));
239 
240  return ptr;
241 }
242 
243 static inline void vis_alignaddr_g0(void *_ptr)
244 {
245  register void *ptr __asm__("g1");
246 
247  ptr = _ptr;
248 
249  __asm__ volatile(".word %2"
250  : "=&r" (ptr)
251  : "0" (ptr),
252  "i" (vis_opc_base | vis_opf(0x18) |
253  vis_rs1_s(1) |
254  vis_rs2_s(0) |
255  vis_rd_s(0)));
256 }
257 
258 static inline void *vis_alignaddrl(void *_ptr)
259 {
260  register void *ptr __asm__("g1");
261 
262  ptr = _ptr;
263 
264  __asm__ volatile(".word %2"
265  : "=&r" (ptr)
266  : "0" (ptr),
267  "i" (vis_opc_base | vis_opf(0x19) |
268  vis_rs1_s(1) |
269  vis_rs2_s(0) |
270  vis_rd_s(1)));
271 
272  return ptr;
273 }
274 
275 static inline void vis_alignaddrl_g0(void *_ptr)
276 {
277  register void *ptr __asm__("g1");
278 
279  ptr = _ptr;
280 
281  __asm__ volatile(".word %2"
282  : "=&r" (ptr)
283  : "0" (ptr),
284  "i" (vis_opc_base | vis_opf(0x19) |
285  vis_rs1_s(1) |
286  vis_rs2_s(0) |
287  vis_rd_s(0)));
288 }
289 
290 #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd)
291 
292 /* Logical operate instructions. */
293 
294 #define vis_fzero(rd) vis_d( 0x60, rd)
295 #define vis_fzeros(rd) vis_s( 0x61, rd)
296 #define vis_fone(rd) vis_d( 0x7e, rd)
297 #define vis_fones(rd) vis_s( 0x7f, rd)
298 #define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd)
299 #define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd)
300 #define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd)
301 #define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd)
302 #define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd)
303 #define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd)
304 #define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd)
305 #define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd)
306 #define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd)
307 #define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd)
308 #define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd)
309 #define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd)
310 #define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd)
311 #define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd)
312 #define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd)
313 #define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd)
314 #define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd)
315 #define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd)
316 #define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd)
317 #define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd)
318 #define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd)
319 #define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd)
320 #define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd)
321 #define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd)
322 #define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd)
323 #define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd)
324 #define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd)
325 #define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd)
326 
327 /* Pixel component distance. */
328 
329 #define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd)
330 
331 #endif /* AVCODEC_SPARC_VIS_H */
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