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44 uint32_t scale_factor[2][8],
47 uint32_t scale_factor[2][8],
51 int nsamples,
int nchannels);
54 int nsamples,
int nchannels);
57 8, 4, 2, 1, 128, 64, 32, 16
61 #define PERM(a, b, c, d) { \
62 (a * 2) + 1, (a * 2) + 0, \
63 (b * 2) + 1, (b * 2) + 0, \
64 (c * 2) + 1, (c * 2) + 0, \
65 (d * 2) + 1, (d * 2) + 0 \
68 #define PERM(a, b, c, d) { \
69 (a * 2) + 0, (a * 2) + 1, \
70 (b * 2) + 0, (b * 2) + 1, \
71 (c * 2) + 0, (c * 2) + 1, \
72 (d * 2) + 0, (d * 2) + 1 \
102 if (
s->increment != 1) {
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
static atomic_int cpu_flags
void ff_sbc_analyze_8_neon(const int16_t *in, int32_t *out, const int16_t *consts)
void ff_sbc_analyze_4_neon(const int16_t *in, int32_t *out, const int16_t *consts)
int ff_sbc_enc_process_input_8s_neon(int position, const uint8_t *pcm, int16_t X[2][SBC_X_BUFFER_SIZE], int nsamples, int nchannels)
int ff_sbc_calc_scalefactors_j_neon(int32_t sb_sample_f[16][2][8], uint32_t scale_factor[2][8], int blocks, int subbands)
void ff_sbc_analyze_4_armv6(const int16_t *in, int32_t *out, const int16_t *consts)
void ff_sbc_analyze_8_armv6(const int16_t *in, int32_t *out, const int16_t *consts)
#define DECLARE_ALIGNED(n, t, v)
uint8_t ff_sbc_input_perm_8[4][8]
int32_t ff_sbcdsp_joint_bits_mask[8]
uint8_t ff_sbc_input_perm_4[2][8]
#define SBC_X_BUFFER_SIZE
av_cold void ff_sbcdsp_init_arm(SBCDSPContext *s)
int ff_sbc_enc_process_input_4s_neon(int position, const uint8_t *pcm, int16_t X[2][SBC_X_BUFFER_SIZE], int nsamples, int nchannels)
#define have_armv6(flags)
void ff_sbc_calc_scalefactors_neon(int32_t sb_sample_f[16][2][8], uint32_t scale_factor[2][8], int blocks, int channels, int subbands)