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33 static void imdct36_blocks_ ## CPU(float *out, float *buf, float *in, int count, int switch_point, int block_type);\
34 void ff_imdct36_float_ ## CPU(float *out, float *buf, float *in, float *win);
53 #if HAVE_6REGS && HAVE_SSE_INLINE
55 #define MACS(rt, ra, rb) rt+=(ra)*(rb)
56 #define MLSS(rt, ra, rb) rt-=(ra)*(rb)
58 #define SUM8(op, sum, w, p) \
60 op(sum, (w)[0 * 64], (p)[0 * 64]); \
61 op(sum, (w)[1 * 64], (p)[1 * 64]); \
62 op(sum, (w)[2 * 64], (p)[2 * 64]); \
63 op(sum, (w)[3 * 64], (p)[3 * 64]); \
64 op(sum, (w)[4 * 64], (p)[4 * 64]); \
65 op(sum, (w)[5 * 64], (p)[5 * 64]); \
66 op(sum, (w)[6 * 64], (p)[6 * 64]); \
67 op(sum, (w)[7 * 64], (p)[7 * 64]); \
70 static void apply_window(
const float *buf,
const float *win1,
71 const float *win2,
float *sum1,
float *sum2,
int len)
74 const float *win1a = win1+
len;
75 const float *win2a = win2+
len;
76 const float *bufa = buf+
len;
77 float *sum1a = sum1+
len;
78 float *sum2a = sum2+
len;
82 "movaps " #a "(%1,%0), %%xmm1 \n\t" \
83 "movaps " #a "(%3,%0), %%xmm2 \n\t" \
84 "mulps %%xmm2, %%xmm1 \n\t" \
85 "subps %%xmm1, %%xmm0 \n\t" \
86 "mulps " #b "(%2,%0), %%xmm2 \n\t" \
87 "subps %%xmm2, %%xmm4 \n\t" \
91 "xorps %%xmm0, %%xmm0 \n\t"
92 "xorps %%xmm4, %%xmm4 \n\t"
103 "movaps %%xmm0, (%4,%0) \n\t"
104 "movaps %%xmm4, (%5,%0) \n\t"
108 :
"r"(win1a),
"r"(win2a),
"r"(bufa),
"r"(sum1a),
"r"(sum2a)
114 static void apply_window_mp3(
float *in,
float *
win,
int *unused,
float *
out,
126 "movaps 0(%0), %%xmm0 \n\t" \
127 "movaps 16(%0), %%xmm1 \n\t" \
128 "movaps 32(%0), %%xmm2 \n\t" \
129 "movaps 48(%0), %%xmm3 \n\t" \
130 "movaps %%xmm0, 0(%1) \n\t" \
131 "movaps %%xmm1, 16(%1) \n\t" \
132 "movaps %%xmm2, 32(%1) \n\t" \
133 "movaps %%xmm3, 48(%1) \n\t" \
134 "movaps 64(%0), %%xmm0 \n\t" \
135 "movaps 80(%0), %%xmm1 \n\t" \
136 "movaps 96(%0), %%xmm2 \n\t" \
137 "movaps 112(%0), %%xmm3 \n\t" \
138 "movaps %%xmm0, 64(%1) \n\t" \
139 "movaps %%xmm1, 80(%1) \n\t" \
140 "movaps %%xmm2, 96(%1) \n\t" \
141 "movaps %%xmm3, 112(%1) \n\t"
142 ::
"r"(in),
"r"(in+512)
155 #define SUMS(suma, sumb, sumc, sumd, out1, out2) \
156 "movups " #sumd "(%4), %%xmm0 \n\t" \
157 "shufps $0x1b, %%xmm0, %%xmm0 \n\t" \
158 "subps " #suma "(%1), %%xmm0 \n\t" \
159 "movaps %%xmm0," #out1 "(%0) \n\t" \
161 "movups " #sumc "(%3), %%xmm0 \n\t" \
162 "shufps $0x1b, %%xmm0, %%xmm0 \n\t" \
163 "addps " #sumb "(%2), %%xmm0 \n\t" \
164 "movaps %%xmm0," #out2 "(%0) \n\t"
168 SUMS( 0, 48, 4, 52, 0, 112)
169 SUMS(16, 32, 20, 36, 16, 96)
170 SUMS(32, 16, 36, 20, 32, 80)
171 SUMS(48, 0, 52, 4, 48, 64)
174 :"
r"(&suma[0]), "
r"(&sumb[0]), "
r"(&sumc[0]), "
r"(&sumd[0])
180 float *out2 =
out + 32 * incr;
185 *
out = -suma[ j] + sumd[16-j];
186 *out2 = sumb[16-j] + sumc[ j];
200 #define DECL_IMDCT_BLOCKS(CPU1, CPU2) \
201 static void imdct36_blocks_ ## CPU1(float *out, float *buf, float *in, \
202 int count, int switch_point, int block_type) \
204 int align_end = count - (count & 3); \
206 for (j = 0; j < align_end; j+= 4) { \
207 LOCAL_ALIGNED_16(float, tmpbuf, [1024]); \
208 float *win = mdct_win_sse[switch_point && j < 4][block_type]; \
212 ff_four_imdct36_float_ ## CPU2(out, buf, in, win, tmpbuf); \
217 for (; j < count; j++) { \
221 int win_idx = (switch_point && j < 2) ? 0 : block_type; \
222 float *win = ff_mdct_win_float[win_idx + (4 & -(j & 1))]; \
224 ff_imdct36_float_ ## CPU1(out, buf, in, win); \
233 DECL_IMDCT_BLOCKS(sse2,
sse)
234 DECL_IMDCT_BLOCKS(sse3,
sse)
235 DECL_IMDCT_BLOCKS(ssse3,
sse)
237 #if HAVE_AVX_EXTERNAL
238 DECL_IMDCT_BLOCKS(avx,avx)
245 for (j = 0; j < 4; j++) {
246 for (
i = 0;
i < 40;
i ++) {
263 #if HAVE_6REGS && HAVE_SSE_INLINE
265 s->apply_window_float = apply_window_mp3;
272 s->imdct36_blocks_float = imdct36_blocks_sse2;
276 s->imdct36_blocks_float = imdct36_blocks_sse3;
279 s->imdct36_blocks_float = imdct36_blocks_ssse3;
282 #if HAVE_AVX_EXTERNAL
284 s->imdct36_blocks_float = imdct36_blocks_avx;
void ff_four_imdct36_float_avx(float *out, float *buf, float *in, float *win, float *tmpbuf)
av_cold void ff_mpadsp_init_x86(MPADSPContext *s)
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
static atomic_int cpu_flags
static float win(SuperEqualizerContext *s, float n, int N)
void ff_dct32_float_sse2(float *out, const float *in)
#define SUM8(op, sum, w, p)
#define INLINE_SSE(flags)
#define LOCAL_ALIGNED_16(t, v,...)
#define EXTERNAL_AVX_FAST(flags)
#define EXTERNAL_SSE3(flags)
void ff_four_imdct36_float_sse(float *out, float *buf, float *in, float *win, float *tmpbuf)
#define DECLARE_ALIGNED(n, t, v)
#define EXTERNAL_SSE2(flags)
#define i(width, name, range_min, range_max)
static void(*const apply_window[4])(AVFloatDSPContext *fdsp, SingleChannelElement *sce, const float *audio)
void ff_dct32_float_avx(float *out, const float *in)
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")
#define EXTERNAL_AVX(flags)
static float mdct_win_sse[2][4][4 *40]
av_cold void ff_mpadsp_init_x86_tabs(void)
float ff_mdct_win_float[8][MDCT_BUF_SIZE]
static int sse(MpegEncContext *s, const uint8_t *src1, const uint8_t *src2, int w, int h, int stride)
#define EXTERNAL_SSSE3(flags)